1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly, to a bootstrap charge pump applicable to a fast motion frequency.
2. Background of the Related Art
As shown in FIG. 1, a related art charge pump circuit is disclosed in U.S. Pat. No. 5,422,586 (Jun. 6, 1995). The charge pump circuit includes NMOS transistors NM11-NM13 serially coupled between a supply voltage Vcc and an output voltage Vout. The drain and the gate of each of the NMOS transistors NM11-NM13 are coupled to each other. At this time, a clock signal CLK1 is applied via a condenser C11 to a source-drain node between the NMOS transistors NM11, NM12. Another clock signal CLK2 is applied by another condenser C12 to a source-drain node between the NMOS transistors NM12, NM13.
The operation of the related art charge pump circuit of FIG. 1 will now be described. When the supply voltage Vcc is supplied, the NMOS transistor NM11 is turned on. A voltage Vcc-Vth (i.e., Vth is a threshold voltage of an NMOS transistor) is charged in the condenser C11, and the NMOS transistor NM12 is turned off.
As shown in FIG. 2A, when a high level clock CLK1 is supplied, the voltage in the condenser C11 is pumped from a value of Vcc-Vth to a value of 2Vcc. The NMOS transistor NM11 is turned off, and the NMOS transistor NM12 is turned on in accordance with the pumped value of 2Vcc, respectively. Then, the value of 2Vcc is charged in the condenser C12.
As shown in FIG. 2B, when a high level clock CLK2 is supplied, the voltage in the condenser C12 is pumped from a value of 2Vcc to a value of 3Vcc. The NMOS transistor NM13 is turned on in accordance with the pumped value of 3Vcc, and the value of 3Vcc is outputted through the output terminal Vout.
Then, when the clock signal CLK1 is in a low level, the NMOS transistor NM12 is turned off, and the NMOS transistor NM11 is turned on. The charging operation of the condenser C12 is completed, and a charging operation of the condenser C11 starts again. The above-described steps are repeatedly carried out.
However, in the related art charge pump circuit, when the voltage pumped through the NMOS transistors NM11-NM13, there may occur a voltage drop as much as the threshold voltage in the NMOS transistors NM1-NM13. Therefore, assuming that the number of pumping groups is N, the final output voltage Vout is obtained by (N+1).times.(Vcc-Vth). Accordingly, a pumping efficiency becomes extremely deteriorated during a low voltage operation.
Another related art example, FIG. 3 illustrates a charge pump circuit for reinforcing a pumping voltage drop by use of a threshold voltage. As shown in FIG. 3, the charge pump circuit includes NMOS transistors NM31-NM34 serially coupled between a supply voltage Vcc and an output voltage Vout. The NMOS transistors NM35-NM37 are sequentially provided between drains and gates of the NMOS transistors NM31-NM33.
At this time, a clock signal CLK4 (PHASE 4) is applied to each of the gates of the NMOS transistors NM31, NM33 via a corresponding one of condensers C34, C36, and a clock signal CLK2 (PHASE 2) is applied to the gate of the NMOS transistor NM32 via a condenser C35. The clock signal CLK1 (PHASE 1) is applied via each of the condensers C31, C33 to the drains of the NMOS transistors NM34, NM36 and to the gates of the NMOS transistors NM35, NM37. The clock signal CLK3 CHASE 3) is applied to the drain of the NMOS transistor NM33 and to the gate of the NMOS transistor NM36 via the condenser C32.
The operation of the related art charge pump circuit of FIG. 3 will now be described. When the supply voltage Vcc is supplied, and high level signals CLK3, CLK4 are inputted via a clock terminal as shown in FIGS. 4B and 4D, the NMOS transistors NM31, NM36 are turned on, to charge a Vcc level voltage in the condensers C31, C35. When a high level clock signal CLK1 as shown in FIG. 4A is inputted, the voltage in the condenser C31 is pumped to 2Vcc, and the pumped value of 2Vcc is charged in the condenser C35 via the NMOS transistor NM36 to turn on the NMOS transistor NM32. Consequently, the 2Vcc voltage pumped in the condenser C31 is charged in the condenser C32.
When the clock signal CLK3 is transmitted to a low level, the NMOS transistor NM36 is turned off, which maintains a charged state of the condenser C35. When the clock signal CLK2 is inputted in a high level as shown in FIG. 4C, the gate voltage of the NMOS transistor NM32 is precharged to about 3Vcc in accordance with the pumping operation of the condenser C35. As a result, the gate voltage 3Vcc of the NMOS transistor NM32 becomes higher than that of the drain voltage 2Vcc, so that the NMOS transistor NM32 is turned on without a voltage drop of Vth.
Therefore, the voltage value of 2Vcc is charged in the condenser C32 by use of the NMOS transistor NM32 of the 2Vcc voltage pumped by the condenser C31. Further, the condenser C36 is turned on and charged in a 2Vcc level through the turned-on NMOS transistor NM37. When the clock signal CLK2 is again transmitted in a low level, the gate voltage of the NMOS transistor NM32 is dropped to 2Vcc for thereby turning off the respective NMOS transistors NM32, NM36. That is, the NMOS transistors NM32, NM36 are turned off faster than the time in which the clock signal CLK1 is turned to a low state.
Also, when the clock signal CLK3 is turned to a high level, the voltage in the condenser C32 is pumped to a voltage value of 3Vcc, and the pumped voltage of 3Vcc is charged in the condenser C36 via the turned-on NMOS transistor NM37. At this time, when a high level clock signal CLK4 is supplied, the gate voltage of the NMOS transistor NM33 becomes precharged to about 4Vcc in accordance with the pumping operation of the condenser C36. As a result, the gate voltage 4Vcc of the NMOS transistor NM33 becomes higher than the drain voltage of 3Vcc to turn on the NMOS transistor NM33 within a range in which the voltage drop of Vth does not occur.
Therefore, when the voltage value of 3Vcc pumped by the condenser C32 is charged in the condenser C33 via the turned-on NMOS transistor NM33. The clock signal CLK4 is transmitted to a low level and the gate voltage of the NMOS transistor NM33 is dropped to 3Vcc to turn off the respective NMOS transistors NM33, NM37. When the clock signal CLK1 is transmitted to a high level, the voltage in the condenser C33 is pumped to 4Vcc and outputted through the turned-on NMOS transistor NM34.
As shown in FIG. 3, when the number N of the pumping groups is three (3), and the supply voltage Vcc is 4.4V, the final output voltage Vout for being outputted through a output terminal becomes 17.1V, whereby the pumping voltage is not dropped by the threshold voltage Vth of the respective NMOS transistors NM31-NM34. The above-described steps are repeatedly carried out for pumping operation of the related art charge pump circuit of FIG. 3.
However, although the related art charge pump circuit as shown in FIG. 3 confines the voltage drop caused by the threshold voltage of the NMOS transistors, the four kinds of clock signals complicate the operating steps. In particular, because the pumped voltage is transferred to a next pumping group only when the clock signals CLK2, CLK4 are in high level, it has been difficult to transfer the pumped voltage during operation in a fast motion frequency.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.